1. Field of the Invention
The present invention relates to integrated circuit manufacturing, and more particularly to insulated-gate field-effect transistors.
2. Description of Related Art
An insulated-gate field-effect transistor (IGFET), such as a metal-oxide semiconductor field-effect transistor (MOSFET), uses a gate to control an underlying surface channel joining a source and a drain. The channel, source and drain are located in a semiconductor substrate, with the source and drain being doped oppositely to the substrate. The gate is separated from the semiconductor substrate by a thin insulating layer such as a gate oxide. The operation of the IGFET involves application of an input voltage to the gate, which sets up a transverse electric field in order to modulate the longitudinal conductance of the channel.
Polysilicon (also called polycrystalline silicon, poly-Si or poly) thin films have many important uses in IGFET technology. One of the key innovations is the use of heavily doped polysilicon in place of aluminum as the gate. Since polysilicon has the same high melting point as a silicon substrate, typically a blanket polysilicon layer is deposited prior to source and drain formation, and the polysilicon is anisotropically etched to provide a gate. Thereafter, the gate provides an implant mask during the formation of source and drain regions by ion implantation, and the implanted dopants are driven-in and activated using a high-temperature anneal that would otherwise melt the aluminum.
An important parameter in IGFETs is the threshold voltage (V.sub.T), which is the minimum gate voltage required to induce the channel to conduct. In general, the positive gate voltage of an N-channel device must be larger than some threshold voltage before a conducting channel is induced, and the negative gate voltage of a P-channel device must be more negative than some threshold voltage to induce the required positive charge (mobile holes) in the channel. There are, however, exceptions to this general rule. For example, depletion-mode devices already have a conductive channel with zero gate voltage, and therefore are normally on. With N-channel depletion-mode devices a negative gate voltage is required to turn the devices off, and with P-channel depletion-mode devices a positive gate voltage is required to turn the devices off
As IGFET dimensions are reduced and the supply voltage remains constant (e.g., 3V), the electric field in the channel near the drain tends to increase. If the electric field becomes strong enough, it can give rise to so-called hot-carrier effects. For instance, electrons can overcome the potential energy barrier between the substrate and the gate insulator thereby causing hot carriers to become injected into the gate insulator. Trapped charge in the gate insulator due to injected hot carriers accumulates over time and can lead to a permanent change in the threshold voltage of the device.
A number of techniques have been utilized to reduce hot carrier effects. One such technique is a lightly doped drain (LDD). The lightly doped drain reduces hot carrier effects by reducing the maximum lateral electric field. The drain is typically doped using two ion implants. A light implant is self-aligned to the gate, and a heavy implant is self-aligned to spacers adjacent to opposing sidewalls of the gate. The spacers are typically oxides or nitrides. The purpose of the lighter dose is to form a lightly doped region of the drain at the edge near the channel. The heavier dose forms a low resistivity heavily doped region of the drain. Since the heavily doped region is farther away from the channel than a conventional drain structure, the depth of the heavily doped region can be made somewhat greater without adversely affecting the device characteristics.
A known fabrication sequence includes implanting lightly doped source/drain regions using the gate as an implant mask, forming the spacers, and implanting heavily doped source/drain regions using the gate and spacers as an implant mask. Another known fabrication sequence includes forming disposable spacers, implanting heavily doped source/drain regions using the gate and spacers as an implant mask, removing the spacers, and implanting lightly doped source/drain regions (between the heavily doped source/drain regions and the gate) using the gate as an implant mask.
A drawback of lightly doped source and drain regions is that their light doping levels increase parasitic resistance. During operation, this parasitic resistance decreases drain current and switching speeds. Therefore, while the lightly doped drain should be large enough to adequately reduce hot carrier effects, the lightly doped source and drain should not be larger than necessary since this increases parasitic resistance.
Complementary metal-oxide semiconductor (CMOS) circuits include N-channel and P-channel devices. During CMOS manufacturing, the gates for the N-channel and P-channel devices are typically formed by depositing a blanket layer of polysilicon over the substrate, forming a photoresist layer over the polysilicon layer, etching and removing portions of the polysilicon layer beneath openings in the photoresist layer, and stripping the photoresist layer. Thereafter, the spacers for the N-channel and P-channel devices are typically formed by depositing a blanket layer of spacer material over the substrate, and then applying an anisotropic etch. Arsenic and/or phosphorus are often used to dope the source and drain for the N-channel device, and boron is often used to dope the source and drain for the P-channel device. Since the gates for the N-channel and P-channel devices typically have identical thicknesses, the spacers for the N-channel and P-channel devices typically have identical sizes.
Boron, however, tends to diffuse into silicon more rapidly than phosphorus and far more rapidly than arsenic during high temperature processing. As a result, after the lightly and heavily doped source and drain regions are implanted into the N-channel and P-channel devices, as the high-temperature anneal is applied to drive-in and activate the implanted dopants, the heavily doped source and drain regions for the P-channel device tend to exhibit far more lateral diffusion than the heavily doped source and drain regions for the N-channel device. This can result in smaller lightly doped source and drain regions for the P-channel device than for the N-channel device. Accordingly, complications may arise with obtaining lightly doped source and drain regions having the desired size for both the N-channel and P-channel devices.
For instance, if the spacers are relatively large, then the lightly doped source and drain regions for the P-channel device may be suitably sized, but the lightly doped source and drain regions for the N-channel device may be larger than necessary, resulting in increased parasitic resistance that decreases drive current and switching speeds. On the other hand, if the spacers are relatively small, then the lightly doped source and drain regions for the N-channel device may be suitably sized, but the lightly doped source and drain regions for the P-channel device may be smaller than desired, resulting in increased hot carrier effects that disrupt the threshold voltage.
Furthermore, a problem encountered in P-channel devices with polysilicon gates containing a high concentration of boron is that when a thin gate oxide is used, poor threshold voltage control may arise due to unwanted boron penetration into the gate oxide, or further, into the underlying channel region. It is reported that boron will penetrate gate oxides that are less than 125 angstroms thick during a 900.degree. C. 30-minute post-implant anneal in nitrogen. It has also been found that the presence of fluorine in the gate oxide worsens the boron penetration problem. Such fluorine can be introduced into the gate oxide if boron difluoride (BF.sub.2) is the implant species. Unfortunately, in some instances, the boron penetration may severely disruption the threshold voltage.
Nitrided oxides and reoxidized nitrided oxides have been used to reduce boron penetration. Likewise, nitrogen has been implanted into gate oxides to reduce boron penetration. For instance, a heavy nitrogen dose (1.times.10.sup.15 atoms/cm.sup.2) can result in the gate oxide incorporating high concentrations of nitrogen that suppress boron penetration of the gate oxide. There are, however, drawbacks to these approaches. For instance, NH.sub.3 nitridation incorporates hydrogen in the oxide, which increases electron trapping in the oxide. Reoxidized nitrided oxide is unable to eliminate the nitridation induced electron traps. Although electron trapping can be reduced by using a very light nitridation, the resulting oxide does not show sufficient resistance to boron penetration. Similarly, N.sub.2 O nitrided and N.sub.2 O grown oxides may not contain sufficient nitrogen to prevent boron penetration. Finally, implanting nitrogen into the gate oxide may not achieve the desired nitrogen concentration in the gate oxide, particularly as the gate oxide becomes extremely thin.
Accordingly, a need exists for an improved method of making N-channel and P-channel IGFETs that provides improved control over the sizes of lightly doped source and drain regions and reduces boron penetration.